Conventional optical projection lithography has been the standard silicon patterning technology for the past 20 years. It is an economical process due to its inherently high throughput, thereby providing a desirable low cost per part or die produced. A considerable infrastructure (including steppers, photomasks, resists, metrology, etc.) has been built up around this technology.
In this process, a photomask, or “reticle”, includes a semiconductor circuit layout pattern typically formed of opaque chrome, on a transparent glass (typically SiO2) substrate. A stepper includes a light source and optics that project light coming through the photomask to image the circuit pattern, typically with a 4× to 5× reduction factor, on a photo-resist film formed on a wafer. The term “chrome” refers to an opaque masking material that is typically but not always comprised of chrome. The transmission of the opaque material may also vary such as in the case of an attenuating phase shift mask.
The process of making the photomask begins by receiving data from a design database. The design database contains data describing at least a portion of an integrated circuit design layout, referred to as the “drawn” pattern, which generally provides a target pattern that the designers wish to achieve on the wafer. Techniques for forming design databases are well known in the art.
After receiving the design database, mask makers form one or more photomasks that can be used to implement the target pattern described by the design data. This mask making process may generally include generating mask pattern data describing initial photomask patterns for forming device features. The initial photomask patterns are formed by employing various resolution enhancement techniques. The resolution enhancement techniques can include splitting the drawn pattern so that it is patterned using two or more photomasks, such as a phase shift mask and a trim mask, for use in a phase shift process (altPSM). Methods for forming phase and trim patterns from design data are well known in the art.
After the initial photomask patterns are formed, a proximity correction process is carried out that corrects the mask pattern data for proximity effects. The proximity correction process generally involves running proximity correction software to perform calculations that alter the shape of the initial photomask pattern to take into account proximity effects, such as optical diffraction effects that occur during the imaging process. In this method, a computer simulation program is often used to compute image-like model values that are taken to represent the features formed for a particular photomask feature pattern or group of patterns. Based on these simulated model values, the photomask pattern can be altered and then simulated again to determine if the altered pattern will improved the printed features. This process can be repeated until the result is with desired specifications. The features added to a photomask pattern based on this procedure are called optical proximity correction features.
As device features continue to shrink, it has become more and more difficult for mask makers to implement the target patterns contained in the design database. These difficulties are generally due to spatial bandwidth constraints of modern lithography systems, and the inherent difficulties associates with forming patterns approaching a nanometer scale (e.g., such as patterns having a critical dimension of 90 nm or less). In the past, these problems have been dealt with by setting appropriate design rules that designers can follow to form a design having target patterns that can be successfully implemented. However, the design rules have become increasingly complex, and often result in complicated patterns in the target design that are difficult or impossible to implement.
Given the overly complicated patterns formed by designers, mask makers are forced to redraw the target patterns to allow them to be implemented, while still maintaining the intended functionality of the circuit design. However, this can be a difficult and time consuming process due to the enormous amount of data that must be culled through by the mask makers. The overly complicated designs formed by the designers merely add to the confusion by making it difficult for the mask makers to determine the intended functionality of devices that must be redrawn. In addition, it is becoming more difficult to program the proximity correction software to successfully handle the complicated designs and produce photomask target patterns that will result in the desired target patterns set by the designers.
Some portions of an integrated circuit design are more complicated than other portions. For example, some memory devices, such as SRAM and DRAM devices can be formed by simply repeating small bit cells a large number of times. It has been found that SRAM and DRAM portions of a circuit can be formed without contact pads by precisely positioning contacts. Thus, gate structures for SRAM and DRAM portions of an integrated circuit are known to be formed without contact pads. These contacts are sometimes centered on a gate, but are sometimes also used to connect the gate to an active region by forming the contact to overlap an edge of the gate to thereby contact the active region.
Portions of semiconductor devices other than SRAM and DRAM, such as the logic portions of a device, are generally far more complicated. Attempting to specifically position contacts in a desired gate contact location without contact pads, as is done in SRAM and DRAM devices, would be very difficult given such complicated design layouts, and would also increase the amount of wafer real estate used to implement a design to allow for precise positioning of the contacts.
Accordingly, methods for simplifying circuit designs and/or allowing for a decrease in wafer real estate employed to make a given circuit would be a welcome addition in the art. Methods for more efficiently forming target patterns that can be implemented would also be desirable improvements, as would methods for improving the communication between circuit designers and mask makers regarding the intended functionality of circuit designs.